top of page

My Approach

I am a contract Quality Manager specializing in semiconductor technology, reliability and new product qualification, and providing resource across several disciplines, drawing upon 40+ years in the industry, and tapping into SME associates that cover a diverse landscape for clients who prefer to outsource for SMEs in the areas of statistics, data analytics, reliability engineering, semiconductor manufacturing oversight, and new product qualification. Clients have engaged me as a contract Quality Manager to advise their business in, for example, preparation for ISO certification, or in the application of QMS methods to their business.

 

I am an evangelist for application of structured problem solving and continuous improvement methods such as 8D, KTA, and 4-QUAD reporting using ANOVA.

​

​Since the inception of my consulting business in 2019, clients have spanned the landscape of semiconductor and solid state devices from design through the manufacturing and the OSAT value chain worldwide, as well as clients who utilize me for industry surveillance and advice to business operations from my technical/technology perspective.

 

PhD in Electrical Engineering from Carnegie-Mellon University.

David J Leary 2.png

David Leary

TECHNICAL ADVISOR & CONSULTANT

Technical advisor to the Semiconductor Industry since 2019 specializing in Silicon Reliability and International Compliance Standards. Providing Contract QMS-based Quality Manager and technical support to Sales and Product Development Engineering teams across the semiconductor products landscape.

​

“I connect my clients with information and insights, that favorably, and sometimes dramatically, impacts their schedules and bottom line profitability.”

​

SERVICES

SERVICES

Services are contracted, projects are closed-ended, deliverables-based, and work-breakdown organized, usually by minimum-hour retainer with monthly reporting and billing. Fees are hourly or by project and follow IEEE Market Measure guidance.

  • QMS-base Quality Manager services

  • Semiconductor physics resource to Reliability engineering

  • Technical editing and EDCS management specializing in Adobe Acrobat Pro, FrameMaker and MS Word

  • Semiconductor industry compliance standards expertise

  • New Product qualification planning and advice on turnkey 3rd party services

  • Tableau-AI for data analytics applied to such areas as test yield, and component-level product returns

  • Tools and training for QMS reporting, product reliability (FIT and MTBF) and yield calculation and reporting

  • Industry surveillance

My services include being a resource for visibility to recently updated and new standards from leading International Standards Associations.

 

With this knowledge, I am in a unique position to advise a client on which standards are applicable to their business, how to apply them, and how to engage directly with the standards body.

​

My Associates add their SME credentials to broaden the scope of what is offered, with the following examples:

  • IC Test development resource to Manufacturing engineering

  • Wafer fab analytics of in-line, EOL, and probe yield

  • Packaging technology development

  • IT support for reporting and applications development

  • Presentations and training

“I value communication and clarity. I draw upon my industry network to obtain a diverse perspective and opinion, which I include in reports that I write for clients, and in my blog articles.”

PROFESSIONAL ORGANIZATIONS

PROFESSIONAL ORGS

David is an Emeritus member of the Council of Science Editors.  He is a technical editor for publications of the JEDEC Solid State Technology Association, and has edited publications of the EOS/ESD Association, the Industry Council on ESD Target Levels, the Institute for Printed Circuits, and the Electronic Industry Association. 

​

David is a member/subscriber of IEEE, ISO, the Fab Economics Consultancy Group, the American National Standards Institute, Semiconductor Engineering, Semiconductor Industry, Semiconductor Manufacturing, and the Semiconductor Professionals Group.

SE.png
ESD.png
EIA.png
jedec.png
IPC.png
SPG.png
ANSI.png

PUBLICATIONS

PUBLICATIONS

​Some of David's publications as a consultant are available at ResearchGate. Below is a cross-sectional view of some of his white papers and conference presentations:

  • “New Product Qualification Considerations for Transistor Gate-All-Around (GAA) Silicon Technology,” January 2024

  • “Qualification Requirements for Non-Volatile Memories - Chamber Temperature Settings Application Note,” September 2023

  • “Overcoming Challenges of HTOL Bias-Life Testing of High-Power ASIC, a 500-Watt 7nm ASIC Case Study,” April 2023

  • “Explicit Design for Power Delivery and Heat Dissipation has Become Critical at Latest Silicon Technology Nodes,” February 2023

  • “FinFET Leakage Behavior and Implications to HTOL Stress Testing,” Nov 2022

  • “Reliability Model Applicable to a 7nm Monolithic Die ASSP - Bias-Life Stress conditions (HTOL) Required to Demonstrate Reliability,” August 2022

  • “SiC Transistor High Power Switching - Qualification Standards,” May 2022

  • “FinFET Leakage Behavior and Implications to HTOL Stress Testing,” March 2022

  • “FinFET and Advanced Packaging Trends, a Reliability and Manufacturability Perspective,” December 2020

  • “Bias-Stress Testing of High-Power Integrated Circuits: HTOL and ORM,” TestConX Mesa AZ, March 2020

  • “Summary of BTI Characteristics for HTOL Planning for Demonstrating ASIC Product 10-year Reliability,” July 2019

  • “The Case for a New HTOL Methodology for High Power ASICs,” April 2019

bottom of page